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Paper submitted to Euromicro Symposium on Digital Systems Design (DSD), Belek-Antalya, Turkey, 2003. ; A model of an exact arithmetic processing is presented. We describe a representation format that gives us a greater expressive capability and covers a wider numerical set. The rational numbers are represented by means of fractional notation and explicit codification of its periodic part. We also give a brief description of exact arithmetic operations on the proposed format. This model constitutes a good alternative for the symbolic arithmetic, in special when numerical exact values are required. As an example, we show an application of the exact numerical processing to calculate the perpendicular vector to another one for aerospace purposes. ; This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government.

Paper submitted to 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Sharjah, Emiratos Árabes, 2003. ; A new conception of flexible calculation that allows us to adjust a sum depending on the available time computation is presented. More specifically, the objective is to obtain a calculation model that makes the processing time/precision more flexible. The addition method is based on carry-select scheme adder and the proposed design uses precalculated data stored in look-up tables, which provide, above all, quality results and systematization in the implementation of low level primitives that set parameters for the processing time. We report an evaluation of the architecture in area, delay and computation error, as well as a suitable implementation in FPGA to validate the design. ; This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government.

Since radix-10 arithmetic has been gaining renewed importance over the last few years, high performance decimal systems and techniques are highly demanded. In this paper, a modification of the CORDIC method for decimal arithmetic is proposed so as to improve calculations. The algorithm works with BCD operands and no conversion to binary is needed. A significant reduction in the number of iterations in comparison to the original decimal CORDIC method is achieved. The experiments showing the advantages of the new method are described. Also, the results with regard to delay obtained by means of an FPGA implementation of the method are shown. ; This work has been supported by the Valencia Region Government (Spain) under Grant No. GV/2007/173.

Paper submitted to the XVIII Conference on Design of Circuits and Integrated Systems (DCIS), Ciudad Real, España, 2003. ; A new conception of flexible calculation that allows us to adjust an operation depending on the available time computation is presented. The proposed arithmetic unit is based on this principle. It contains a control operation module that determines the process time of each calculation. The operation method design uses precalculated data stored in look-up tables, which provide, above all, quality results and systematization in the implementation of low level primitives that set parameters for the processing time. We report an evaluation of the architecture in area, delay and computation error, as well as a suitable implementation in FPGA to validate the design. ; This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government.

Paper submitted to the IFIP International Conference on Very Large Scale Integration (VLSI-SOC), Darmstadt, Germany, 2003. ; A new operation model of flexible calculation that allows us to adjust the operation delay depending on the available time is presented. The operation method design uses look-up tables and progressive construction of the result. The increase in the operators' granularity opens up new possibilities in calculation methods and microprocessor design. This methodology, together with the advances in technology, enables the functions of an arithmetic unit to be implemented on the basis of techniques based on stored data that provide quality results and systematization in the implementation. The proposed techniques are applied in the design of a multiplier operator. We report an evaluation of the architecture in area, delay and computation error, as well as a suitable implementation of an application example in FPGA to validate the design. ; This work is being backed by grant DPI2002-04434-C04-01 from the Ministerio de Ciencia y Tecnología of the Spanish Government.