The timing verification of real-time single core systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes of the individual tasks, including the ETB, are studied from the system level perspective. The transition between those two steps involves accounting for the interference effects that arise when tasks contend for access to shared resource. The advent of multicore processors challenges the viability of this two-step approach because several complex contention effects at the processor level arise that cause tasks to be unable to make progress while actually holding the CPU, which are very difficult to tightly capture by simply inflating the tasks' ETB. In this paper we show how contention on access to hardware shared resources creates a circular dependence between the determination of tasks' ETB and their scheduling at runtime. To help loosen this knot we present an approach that acknowledges different flavors of time compos ability, examining in detail the variant intended for partitioned scheduling, which we evaluate on two real processor boards used in the space domain. ; The research leading to this work has received funding from: the European Union's Horizon 2020 research and innovation programme under grant agreement No 644080(SAFURE); the European Space Agency under Contract 789.2013; and COST Action IC1202, Timing Analysis On Code-Level (TACLe). This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant TIN2012-34557. Jaume Abella has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717. ; Peer Reviewed ; Postprint (author's final draft)
The timing verification of real-time single core systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes of the individual tasks, including the ETB, are studied from the system level perspective. The transition between those two steps involves accounting for the interference effects that arise when tasks contend for access to shared resource. The advent of multicore processors challenges the viability of this two-step approach because several complex contention effects at the processor level arise that cause tasks to be unable to make progress while actually holding the CPU, which are very difficult to tightly capture by simply inflating the tasks' ETB. In this paper we show how contention on access to hardware shared resources creates a circular dependence between the determination of tasks' ETB and their scheduling at runtime. To help loosen this knot we present an approach that acknowledges different flavors of time compos ability, examining in detail the variant intended for partitioned scheduling, which we evaluate on two real processor boards used in the space domain. ; The research leading to this work has received funding from: the European Union's Horizon 2020 research and innovation programme under grant agreement No 644080(SAFURE); the European Space Agency under Contract 789.2013; and COST Action IC1202, Timing Analysis On Code-Level (TACLe). This work has also been partially supported by the Spanish Ministry of Science and Innovation under grant TIN2012-34557. Jaume Abella has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717. ; Peer Reviewed ; Postprint (author's final draft)
As implementation technology shrinks, the presence of errors in cache memories is becoming an increasing issue in all computing domains. Critical systems, e.g. space and automotive, are specially exposed and susceptible to reliability issues. Furthermore, hardware designs in these systems are migrating to multilevel cache multicore systems, in which write-through first level data (DL1) caches have been shown to heavily harm average and guaranteed performance. While write-back DL1 caches solve this problem they come with their own challenges: they need Error Correction Codes (ECC) to tolerate soft errors, but implementing DL1 ECC in simple embedded micro-controllers requires either complex hardware to squash instructions consuming erroneous data, or delayed delivery of data to correct potential errors, which impacts performance even if such process is pipelined. In this paper we present a low-complexity hardware mechanism to anticipate data fetch and error correction in DL1 so that both (1) correct data is always delivered, but (2) avoiding additional delays in most of the cases. This achieves both high guaranteed performance and an effective solutions against errors. ; This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P, the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No. 772773) and the HiPEAC Network of Excellence. Pedro Benedicte and Jaume Abella have been partially supported by the MINECO under FPU15/01394 grant and Ramon y Cajal postdoctoral fellowship number RYC-2013-14717 respectively. ; Peer Reviewed ; Postprint (author's final draft)
As implementation technology shrinks, the presence of errors in cache memories is becoming an increasing issue in all computing domains. Critical systems, e.g. space and automotive, are specially exposed and susceptible to reliability issues. Furthermore, hardware designs in these systems are migrating to multilevel cache multicore systems, in which write-through first level data (DL1) caches have been shown to heavily harm average and guaranteed performance. While write-back DL1 caches solve this problem they come with their own challenges: they need Error Correction Codes (ECC) to tolerate soft errors, but implementing DL1 ECC in simple embedded micro-controllers requires either complex hardware to squash instructions consuming erroneous data, or delayed delivery of data to correct potential errors, which impacts performance even if such process is pipelined. In this paper we present a low-complexity hardware mechanism to anticipate data fetch and error correction in DL1 so that both (1) correct data is always delivered, but (2) avoiding additional delays in most of the cases. This achieves both high guaranteed performance and an effective solutions against errors. ; This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P, the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No. 772773) and the HiPEAC Network of Excellence. Pedro Benedicte and Jaume Abella have been partially supported by the MINECO under FPU15/01394 grant and Ramon y Cajal postdoctoral fellowship number RYC-2013-14717 respectively. ; Peer Reviewed ; Postprint (author's final draft)
A letter report issued by the General Accounting Office with an abstract that begins "The Veterans Benefits Administration (VBA) developed a computer-assisted training program, known as the Training and Performance Support System (TPSS), to help its employees become more accurate in processing disability compensation and pension claims. The program seeks to provide uniform and consistent training to employees in 57 regional offices. Although VBA's long-term goal is to attain a 96 percent accuracy rate for claims processing, VBA reported an accuracy rate of only 59 percent for fiscal year 2000. This report reviews (1) the status of the TPSS program's development and implementation and (2) the extent to which TPSS will meet its objectives. GAO found that despite VBA's objective to centrally develop a standardized training program, significant delays in the development of TPSS are hindering the program's ability to provide standardized training to claims processing employees. According to VBA's current schedule, the full development of the program will not be completed until at least 2004, or about two years later than VBA had planned. Although VBA provided nine training modules to regional offices to begin the program, the extent to which the offices implemented them varied considerably. Many offices reported that workload pressures prevented them from fully using the modules. GAO found that TPSS might not fully achieve its objectives. For instance, TPSS training modules may not be available in time to train new employees hired to replace employees who are expected to retire in the future. Furthermore, TPSS may not reduce training time, as envisioned by VBA."
The Audio Typing Unit by IBM was designed to enable visually impaired typists to make revisions and review final copy without the assistance of sighted co-workers. The ability of the unit to do so, based on monitoring the performance of five subjects, is reviewed. The authors state that the unit has a significant impact upon the learning process for visually impaired word processors, and suggest incorporating training on the Audio Typing Unit into vocational rehabilitation programs for blind persons.
Testimony issued by the General Accounting Office with an abstract that begins "To address overfishing, the National Marine Fisheries Service started using individual fishing quotas (IFQ) as a fishery conservation and management tool in 1990. Under an IFQ program, a regional fishery management council sets a maximum, or total allowable catch, and allocates the privilege to harvest a certain portion of the catch in the form of quota to individual vessels, fishermen, or other eligible recipients. IFQ programs have achieved many of the desired conservation and management benefits, such as helping to stabilize fisheries, reducing excessive investment in fishing capacity, and improving safety. However, concerns have been raised about the economic effects of IFQ programs on fish processors and fishing communities, among others. This testimony is based on two GAO reports on issues related to the use of IFQs (Individual Fishing Quotas: Better Information Could Improve Program Management, GAO-03- 159, Dec. 11, 2002, and Individual Fishing Quotas: Methods for Community Protection and New Entry Require Periodic Evaluation, GAO-04-277, Feb. 24, 2004). Specifically, GAO addressed the (1) economic effects of the Alaskan halibut IFQ program on processors and (2) the methods available for protecting communities under an IFQ program."
The study was conducted to determine, analyze, and evaluate the coping mechanisms of the former and current balut processors in Pateros. The general objective of the study was to present the coping mechanisms and diversification options of balut processors in Pateros. The specific objectives were to present the profiles of the existing and former balut processors in Pateros; to trace the development/changes in the actual practices of balut processors over a period of time; to evaluate the coping mechanisms undertaken and diversification decisions made by existing and former balut processors and identify potential problems arising from it; to determine the external and internal factors affecting the sustainability of operations of balut processors; and to recommend possible solutions/strategies based on the findings of the study. A total of 11 balut processors were identified and interviewed. The lists were obtained from the official website of Pateros and from the record of the Business Section of the town's municipality. On the other hand, there were eight former balut processors identified through snowball or referral method. The profile information of the existing and former balut processors were presented such as sex, age educational attainment, household size, number of years of residence, and membership to an organization. The influence of these entrepreneurial characteristics to the type of diversification decisions and coping mechanisms adapted by the processors were analyzed and described. The external factors affecting the balut operations and its sustainability were also identified and analyzed. The external factors were supply of duck eggs, costs of feeds, competition with balut producing provinces and Vietnamese processors, mass production with the aid of modern incubator, government assistance through OTOP and Balut festival, tertiary educational system in Pateros, and aging population. These factors were acting on the balut business that led to the coping mechanisms and diversification decision made by the balut processors. The balut business practices were also presented to trace the changes and development in the business as a response to the changes in the industry's environment. It was done across functional areas; marketing, production, human resource and finance. And to assess the profitability of the diversification decision o trading balut, a cost-benefit analysis was done. The study showed that the target markets of balut are those people with exotic taste. The price of balut was also highly dependent on the price of duck eggs and increasing the price too much would result to a decrease in the consumption of the balut eaters since it was not a necessity good. Pateros also used traditional method in producing balut that gave it the delicious taste. It was also showed in the study that balut making was labor intensive and that there were few people now who were engaged in the balut making. The capital for balut business was also a constant problem to the processors due to the inappropriate allocation of sales between the household needs and business operations. The internal factors affecting the sustainability of the balut operations were also identified and analyzed. The internal factors were seasonal demand, overcapacity and under capacity in production of balut during the peak and lean seasons, skills of the balut processors in handling balut, role of the balutan workers, interest of the entrepreneur, the financial standing of the balut business. Meanwhile, evaluation of the coping mechanisms undertaken and diversification decisions made by the processors was done through the analysis of the advantages and disadvantages of the given business decisions. The coping mechanisms and diversification strategies that were evaluated and analyzed were concentric diversification through selling balut by-products and trading balut, conglomerate diversification through water refilling station and rental building business, price and quality differentiation strategies, forward integration, strategic alliance, product development, market development, and liquidation. Profitability analysis of each strategy was done to determine the earnings gained from the business. It was found out that the processors were able to gain profits but the net margins were low. This was due to different factors such as high price of duck eggs, and labour costs. Analysis on the strengths, weaknesses, opportunities and threats was also done to summarize the internal and external factors acting upon the balut business that consequently affected their coping mechanisms and diversification decisions. The identified strengths of Pateros balut industry were high quality of balut, established name and the traditional method of processing balut while the identified weaknesses were sources of raw materials, seasonal demand and limited product form. On the other hand, the identified opportunities of the industry were the international market, balut festival, OTOP support services, and the local government's plan while the identified threats were competition with other balut-producing provinces, urbanization, and increasing price of poultry feeds. Other concern like the lack of business succession was also included in the analysis. Meanwhile, the problems of the processors were identified such as competition both in the local and domestic markets, sources of raw materials, and oversupply of balut from the suppliers of the processors engaged in trading balut, costly marketing strategies and so on. Recommendations were done to help the processors and the former balut processors to cope with the problems arising from the coping mechanism and diversification decisions made. It was done by stakeholders such as balut processors, government, potential processors, and support agencies. For the balut processors, it was recommended that they perform the market development for the international market and focused strategy for the institutional buyers in the local market since both markets were not fully penetrated by the balut processors in Pateros. For the government, it was recommended that they should assist the balut processors to backward integrate or contract grow to help address the problem in the source of raw materials, for the potential balut processors, it was recommended that they attend trainings on how to process balut ion a traditional method and how to process bottled balut. Lastly, for the support agencies like DOST and DTI, it was recommended that they assist the balut processors in marketing their balut in a greater market reach through conducting different programs like trade fairs that will showcase the Pateros balut.
[EN] In this work, we address the efficient realization of block-Jacobi preconditioning on graphics processing units (GPUs). This task requires the solution of a collection of small and independent linear systems. To fully realize this implementation, we develop a variablesize batched matrix inversion kernel that uses Gauss-Jordan elimination (GJE) along with a variable-size batched matrix-vector multiplication kernel that transforms the linear systems' right-hand sides into the solution vectors. Our kernels make heavy use of the increased register count and the warp-local communication associated with newer GPU architectures. Moreover, in the matrix inversion, we employ an implicit pivoting strategy that migrates the workload (i.e., operations) to the place where the data resides instead of moving the data to the executing cores. We complement the matrix inversion with extraction and insertion strategies that allow the block-Jacobi preconditioner to be set up rapidly. The experiments on NVlDlA's K40 and P100 architectures reveal that our variable-size batched matrix inversion routine outperforms the CUDA basic linear algebra subroutine (cuBLAS) library functions that provide the same (or even less) functionality. We also show that the preconditioner setup and preconditioner application cost can be somewhat offset by the faster convergence of the iterative solver. (C) 2018 Elsevier B.V. All rights reserved. ; This material is based upon work supported by the U.S. Department of Energy Office of Science, Office of Advanced Scientific Computing Research, Applied Mathematics program under Award Number DE-SC-0010042. H. Anzt was supported by the "Impuls and Vernetzungsfond of the Helmholtz Association" under grant VH-NG-1241. G. Flegar and E. S. Quintana-Orti were supported by project TIN2014-53495-R of the MINECO-FEDER; and project OPRECOMP (http://oprecomp.eu) with the financial support of the Future and Emerging Technologies (FET) programme within the European Union's Horizon 2020 research and innovation ...
In real-time systems, the techniques to derive bounds to the contention tasks can suffer in multicore build on resource quota monitoring and enforcement. Existing techniques track and bound the number of requests to hardware shared resources that each core (task) is allowed to perform. In this paper we show that current software-only solutions work well when there is a single resource and type of request to track and bound, but do not scale to the more general case of several shared resources that accept different request types, each with a different associated latency. To handle this (more general) case, we propose low-overhead hardware support called Maximum-Contention Control Unit (MCCU). The MCCU performs fine-grain tracking of different types of requests, preventing a core to cause more interference on its contenders than budgeted. In this process, the MCCU also helps verifying that individual requests duration does not exceed their theoretical bounds, hence dealing with scenarios in which requests can have an arbitrarily large duration. ; This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P, the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No. 772773) and the HiPEAC Network of Excellence. Carles Hernández is jointly funded by the MINECO and FEDER funds through grant TIN2014-60404-JIN. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717. ; Peer Reviewed ; Postprint (author's final draft)
In real-time systems, the techniques to derive bounds to the contention tasks can suffer in multicore build on resource quota monitoring and enforcement. Existing techniques track and bound the number of requests to hardware shared resources that each core (task) is allowed to perform. In this paper we show that current software-only solutions work well when there is a single resource and type of request to track and bound, but do not scale to the more general case of several shared resources that accept different request types, each with a different associated latency. To handle this (more general) case, we propose low-overhead hardware support called Maximum-Contention Control Unit (MCCU). The MCCU performs fine-grain tracking of different types of requests, preventing a core to cause more interference on its contenders than budgeted. In this process, the MCCU also helps verifying that individual requests duration does not exceed their theoretical bounds, hence dealing with scenarios in which requests can have an arbitrarily large duration. ; This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P, the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No. 772773) and the HiPEAC Network of Excellence. Carles Hernández is jointly funded by the MINECO and FEDER funds through grant TIN2014-60404-JIN. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717. ; Peer Reviewed ; Postprint (author's final draft)
A digital-desk pilot program, named One Laptop Per Child (OPLC), in Brazil uses a unique display design to provide an interactive interface developed to enhance education and minimize ergonomic concerns. The one-to-one computer strategy as proposed by Nicholas Negroponte is a way of circumventing the tragedy of the locked computer lab because it gives children full access to computers anytime. The OLPC program has focused on a solution that minimizes power consumption, which also limits the display's maximum size and processor performance because the LCD backlights are responsible for a significant part of the power consumption in laptops. The government has also developed a new type of low-cost tablet that is based on a resistive principle. High transparencies can be obtained in the 90% range in the tablet, while robustness is guaranteed by the outstanding tribological characteristics of Sn02 on glass.
