Suchergebnisse

Producción Científica ; The concept of asymmetric entanglement-assisted quantum error-correcting code (asymmetric EAQECC) is introduced in this article. Codes of this type take advantage of the asymmetry in quantum errors since phase-shift errors are more probable than qudit-flip errors. Moreover, they use pre-shared entanglement between encoder and decoder to simplify the theory of quantum error correction and increase the communication capacity. Thus, asymmetric EAQECCs can be constructed from any pair of classical linear codes over an arbitrary field. Their parameters are described and a Gilbert-Varshamov bound is presented. Explicit parameters of asymmetric EAQECCs from BCH codes are computed and examples exceeding the introduced Gilbert-Varshamov bound are shown. ; This work was supported in part by the Spanish Government MICINN/FEDER grants PGC2018-096446-B-C21, PGC2018-096446-B-C22 and RED2018-102583-T and MINECO grant RYC-2016-20208 (AEI/FSE/UE), Generalitat Valenciana, grant AICO-2019-223, as well as by Universitat Jaume I, grant P1-1B2018-10. Also by the JSPS (Japan) under grant 17K06419 and by the Junta de CyL (Spain) under grant VA166G18.

Abstract. This article explores the a mathematical model of the a data transmission channel with errors grouping. We propose an estimating method for energy gain from coding and energy efficiency of binary codes in channels with grouped errors. The proposed method uses a simplified Bennet and Froelich's model and allows leading the research of the energy gain from coding for a wide class of data channels without restricting the way of the length distributing the error bursts. The reliability of the obtained results is confirmed by the information of the known results in the theory of error-correcting coding in the simplified variant.

Capter 1 Introduction -- 1.1 Properties of Information -- 1.2 Levels of Information -- 1.3 Information Media -- 1.4 Reversible and Irreversible Processes -- I -- Capter 2 Noiseless Channels -- 3 Coding for Noiseless Channels -- 4 Joint Events, Natural Languages -- 5 Noisy Channel -- 6 Error Checking and Correcting Codes -- II -- 7 Properties of Continuous Channels -- Capter 8 Detection of Continuous Signals -- 9 Information Filters -- References -- Appendix A Fourier Transform and Related Concepts -- Appendix B Binary logarithms and Entropies -- Appendix C Problems.

(c) 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. ; [EN] Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption. ; This work was supported in part by the Spanish Government under Project TIN2016-81075-R, and in part by the Primeros Proyectos de Investigacion, Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), Valencia, Spain, under Project PAID-06-18 20190032. ; Saiz-Adalid, L.; Gracia-Morán, J.; Gil ...

[EN] The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word lengths, which do not frequently match those employed in digital systems. This paper focuses on double error correction (DEC) codes for word lengths that are in powers of two (8, 16, 32, and 64), which are commonly used in memories. We also focus on hardware implementations of the encoder and decoder circuits for very fast operations. This work proposes new low redundancy and reduced overhead (LRRO) DEC codes, with the same redundancy as the equivalent BCH DEC codes, but whose encoder, and decoder circuits present a lower overhead (in terms of propagation delay, silicon area usage and power consumption). We used a methodology to search parity check matrices, based on error patterns, in order to design the new codes. We implemented and synthesized them, and compared their results with those obtained for the BCH codes. Our implementation of the decoder circuits achieved reductions between 2.8% and 8.7% in the propagation delay, between 1.3% and 3.0% in the silicon area, and between 15.7% and 26.9% in the power consumption. Therefore, we propose LRRO codes as an alternative for protecting information against multiple errors. ; This research was supported in part by the Spanish Government, project TIN2016-81075-R, by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), project 20190032, and by the Institute of Information and Communication Technologies (ITACA). ; Saiz-Adalid, L.; Gracia-Morán, J.; Gil Tomás, DA.; Baraza Calvo, JC.; Gil, P. (2020). Reducing the Overhead of BCH Codes: New Double Error Correction Codes. Electronics. 9(11):1-14. https://doi.org/10.3390/electronics9111897 ; S ; 1 ; 14 ; 9 ; 11 ; Fujiwara, E. (2005). Code Design for Dependable Systems. doi:10.1002/0471792748 ...

We introduce non-binary IPP set systems with traceability properties that have IPP codes and binary IPP set systems with traceability capabilities as particular cases. We prove an analogue of the Gilbert–Varshamov bound for such systems. ; Marcel Fernandez: The work of M. Fernández has been supported by the Spanish Government Grant TEC2015- 68734-R and Catalan Government Grant SGR 782. ; Peer Reviewed ; Postprint (author's final draft)

New Methods of Concurrent Checking is the ultimate reference to answer the question as to how the best possible state-of-the-art error detection circuits can be designed. The most effective methods of concurrent checking for digital circuits are comprehensively described which were developed in the last 15 years. Some of the methods are published for the first time. How concurrent checking can be combined with soft error correction is also shown for the first time. This book is invaluable in considering the design of reliable systems in the emerging Nanotechnologies with an associated growing number of transient faults. Written by a team of two leading experts and two very successful young former PhD students, New Methods of Concurrent Checking describes new methods of concurrent checking, such as partial duplication, use of output dependencies, complementary circuits, self-dual parity, self-dual duplication and others. A special chapter demonstrates how the new general methods of concurrent checking can be more specifically applied to regular structures to obtain optimum results. This is exemplified for all types of adders up to 64 bits with a level of detail never before presented in the literature. The clearly written text is illustrated by about 100 figures. New Methods of Concurrent Checking is approved in many university courses for graduate and undergraduate students, and it is of interest to students and teachers in electrical engineering and computer science, researchers and designers and all readers who are interested in the design and the understanding of reliable circuits and computers.

This work is the further development of the theory of norms of syndromes: the theory of polynomial invariants of G-orbits of errors expands with the group G of automorphisms of binary cyclic BCH codes obtained by joining the degrees of cyclotomic permutation to the group Γ and practically exhausting the group of automorphisms of BCH codes. It is determined that polynomial invariants, like the norms of syndromes, have a scalar character and are one-to-one characteristics of their orbits for BCH codes with a constructive distance of five. The paper introduces the corresponding vector polynomial invariants for primitive cyclic BCH codes with a constructive distance of seven, next to the norms of the syndromes that are already vector quantities; the basic properties of the vector polynomial invariants are investigated. It is established that the property of mutual unambiguity is violated: there are G-orbit-isomers, which are different, but have the same vector polynomial invariants. It is substantiated and demonstrated by examples that this circumstance greatly complicates error decoding algorithms based on polynomial invariants

Recent work has employed joint typicality encoding and decoding of nested linear code ensembles to generalize the compute-forward strategy to discrete memoryless multiple-access channels (MACs). An appealing feature of these nested linear code ensembles is that the coding strategies and error probability bounds are conceptually similar to classical techniques for random i.i.d. code ensembles. In this paper, we consider the problem of recovering K linearly independent combinations over a K-user MAC, i.e., recovering the messages in their entirety via nested linear codes. While the MAC rate region is well-understood for random i.i.d. code ensembles, new techniques are needed to handle the statistical dependencies between competing codeword K-tuples that occur in nested linear code ensembles. ; Grant numbers : This work was supported by the Spanish Government grant ELISA (TEC2014-59255-C3-1-R).© 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

The research work is partially funded by the Strategic Educational Pathways Scholarship Scheme (STEPS-Malta). This scholarship is partly financed by the European Union - European Social Fund (ESF 1.25). ; Low-Density Parity-Check (LDPC) codes achieve good performance, tending towards the Slepian-Wolf bound, when used as channel codes in Distributed Source Coding (DSC). Most LDPC codes found in literature are designed assuming random distribution of transmission errors. However, certain DSC applications can predict the error location within a certain level of accuracy. This feature can be exploited in order to design application specific LDPC codes to enhance the performance of traditional LDPC codes. This paper proposes a novel architecture for asymmetric DSC where the encoder is able to estimate the location of the errors within the side information. It then interleaves the bits having a high probability of error to the beginning of the codeword. The LDPC codes are designed to provide a higher level of protection to the front bits. Simulation results show that correct localization of errors pushes the performance of the system on average 13.3% closer to the Slepian-Wolf bound, compared to the randomly constructed LDPC codes. If the error localization prediction fails, such that the errors are randomly distributed, the performance is still in line with that of the traditional DSC architecture. ; peer-reviewed