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Producción Científica ; The concept of asymmetric entanglement-assisted quantum error-correcting code (asymmetric EAQECC) is introduced in this article. Codes of this type take advantage of the asymmetry in quantum errors since phase-shift errors are more probable than qudit-flip errors. Moreover, they use pre-shared entanglement between encoder and decoder to simplify the theory of quantum error correction and increase the communication capacity. Thus, asymmetric EAQECCs can be constructed from any pair of classical linear codes over an arbitrary field. Their parameters are described and a Gilbert-Varshamov bound is presented. Explicit parameters of asymmetric EAQECCs from BCH codes are computed and examples exceeding the introduced Gilbert-Varshamov bound are shown. ; This work was supported in part by the Spanish Government MICINN/FEDER grants PGC2018-096446-B-C21, PGC2018-096446-B-C22 and RED2018-102583-T and MINECO grant RYC-2016-20208 (AEI/FSE/UE), Generalitat Valenciana, grant AICO-2019-223, as well as by Universitat Jaume I, grant P1-1B2018-10. Also by the JSPS (Japan) under grant 17K06419 and by the Junta de CyL (Spain) under grant VA166G18.

We introduce non-binary IPP set systems with traceability properties that have IPP codes and binary IPP set systems with traceability capabilities as particular cases. We prove an analogue of the Gilbert–Varshamov bound for such systems. ; Marcel Fernandez: The work of M. Fernández has been supported by the Spanish Government Grant TEC2015- 68734-R and Catalan Government Grant SGR 782. ; Peer Reviewed ; Postprint (author's final draft)

(c) 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. ; [EN] Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption. ; This work was supported in part by the Spanish Government under Project TIN2016-81075-R, and in part by the Primeros Proyectos de Investigacion, Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), Valencia, Spain, under Project PAID-06-18 20190032. ; Saiz-Adalid, L.; Gracia-Morán, J.; Gil ...

[EN] The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word lengths, which do not frequently match those employed in digital systems. This paper focuses on double error correction (DEC) codes for word lengths that are in powers of two (8, 16, 32, and 64), which are commonly used in memories. We also focus on hardware implementations of the encoder and decoder circuits for very fast operations. This work proposes new low redundancy and reduced overhead (LRRO) DEC codes, with the same redundancy as the equivalent BCH DEC codes, but whose encoder, and decoder circuits present a lower overhead (in terms of propagation delay, silicon area usage and power consumption). We used a methodology to search parity check matrices, based on error patterns, in order to design the new codes. We implemented and synthesized them, and compared their results with those obtained for the BCH codes. Our implementation of the decoder circuits achieved reductions between 2.8% and 8.7% in the propagation delay, between 1.3% and 3.0% in the silicon area, and between 15.7% and 26.9% in the power consumption. Therefore, we propose LRRO codes as an alternative for protecting information against multiple errors. ; This research was supported in part by the Spanish Government, project TIN2016-81075-R, by Primeros Proyectos de Investigacion (PAID-06-18), Vicerrectorado de Investigacion, Innovacion y Transferencia de la Universitat Politecnica de Valencia (UPV), project 20190032, and by the Institute of Information and Communication Technologies (ITACA). ; Saiz-Adalid, L.; Gracia-Morán, J.; Gil Tomás, DA.; Baraza Calvo, JC.; Gil, P. (2020). Reducing the Overhead of BCH Codes: New Double Error Correction Codes. Electronics. 9(11):1-14. https://doi.org/10.3390/electronics9111897 ; S ; 1 ; 14 ; 9 ; 11 ; Fujiwara, E. (2005). Code Design for Dependable Systems. doi:10.1002/0471792748 ...

The article explores the syndrome invariants of АГ-group of automorphisms of Reed–Solomon codes (RS-codes) that are a joint group of affine and cyclic permutations. The found real invariants are a set of norms of N Г-orbits that make up one or another АГ-orbit. The norms of Г-orbits are vectors with 2 1 Cδ− coordinates from the Galois field, that are determined by all kinds of pairs of components of the error syndromes. In this form, the invariants of the АГ-orbits were cumbersome and difficult to use. Therefore, their replacement by conditional partial invariants is proposed. These quasi-invariants are called norm-projections. Norm-projection uniquely identifies its АГ-orbit and therefore serves as an adequate way for formulating the error correction method by RS-codes based on АГ-orbits. The power of the АГ-orbits is estimated by the value of N2, equal to the square of the length of the RS-code. The search for error vectors in transmitted messages by a new method is reduced to parsing the АГ‑orbits, but actually their norm-projections, with the subsequent search for these errors within a particular АГ-orbit. Therefore, the proposed method works almost N2 times faster than traditional syndrome methods, operating on the basic of the "syndrome – error" principle, that boils down to parsing the entire set of error vectors until a specific vector is found.

© 2018 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. ; [EN] Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments. One of the main causes of MCUs in space applications is cosmic radiation. A common solution is the use of error correction codes (ECCs). Nevertheless, when using ECCs in space applications, they must achieve a good balance between error coverage and redundancy, and their encoding/decoding circuits must be efficient in terms of area, power, and delay. Different codes have been proposed to tolerate MCUs. For instance, Matrix codes use Hamming codes and parity checks in a bi-dimensional layout to correct and detect some patterns of MCUs. Recently presented, column¿line¿code (CLC) has been designed to tolerate MCUs in space applications. CLC is a modified Matrix code, based on extended Hamming codes and parity checks. Nevertheless, a common property of these codes is the high redundancy introduced. In this paper, we present a series of new lowredundant ECCs able to correct MCUs with reduced area, power, and delay overheads. Also, these new codes maintain, or even improve, memory error coverage with respect to Matrix and CLC codes. ; This work was supported by the Spanish Government under the research Project TIN2016-81075-R. ; Gracia-Morán, J.; Saiz-Adalid, L.; Gil Tomás, DA.; Gil, P. (2018). Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26(10):2132-2142. https://doi.org/10.1109/TVLSI.2018.2837220 ; S ; 2132 ; 2142 ...

2132 2142 26 10 ; S ; © 2018 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. [EN] Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments. One of the main causes of MCUs in space applications is cosmic radiation. A common solution is the use of error correction codes (ECCs). Nevertheless, when using ECCs in space applications, they must achieve a good balance between error coverage and redundancy, and their encoding/decoding circuits must be efficient in terms of area, power, and delay. Different codes have been proposed to tolerate MCUs. For instance, Matrix codes use Hamming codes and parity checks in a bi-dimensional layout to correct and detect some patterns of MCUs. Recently presented, column¿line¿code (CLC) has been designed to tolerate MCUs in space applications. CLC is a modified Matrix code, based on extended Hamming codes and parity checks. Nevertheless, a common property of these codes is the high redundancy introduced. In this paper, we present a series of new lowredundant ECCs able to correct MCUs with reduced area, power, and delay overheads. Also, these new codes maintain, or even improve, memory error coverage with respect to Matrix and CLC codes. This work was supported by the Spanish Government under the research Project TIN2016-81075-R. Gracia-Morán, J.; Saiz-Adalid, L.; Gil Tomás, DA.; Gil, P. (2018). Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 26(10):2132-2142. https://doi.org/10.1109/TVLSI.2018.2837220

Measurement errors in predictor variables bias multiple regression coefficients, and the problem is particularly complex with nonlinear models containing product variates. This article presents formulas and computing algorithms for correcting data before regression analyses in order to eliminate biases due to measurement errors in models with second- and third-order product variates (e.g., YZ and XYZ). The method requires independent estimates of error variances and covariances for the first-order variates (e.g., X, Y, and Z). An analysis of empirical data illustrates the approach. Errors in estimates are examined through Monte Carlo analyses.

As implementation technology shrinks, the presence of errors in cache memories is becoming an increasing issue in all computing domains. Critical systems, e.g. space and automotive, are specially exposed and susceptible to reliability issues. Furthermore, hardware designs in these systems are migrating to multilevel cache multicore systems, in which write-through first level data (DL1) caches have been shown to heavily harm average and guaranteed performance. While write-back DL1 caches solve this problem they come with their own challenges: they need Error Correction Codes (ECC) to tolerate soft errors, but implementing DL1 ECC in simple embedded micro-controllers requires either complex hardware to squash instructions consuming erroneous data, or delayed delivery of data to correct potential errors, which impacts performance even if such process is pipelined. In this paper we present a low-complexity hardware mechanism to anticipate data fetch and error correction in DL1 so that both (1) correct data is always delivered, but (2) avoiding additional delays in most of the cases. This achieves both high guaranteed performance and an effective solutions against errors. ; This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P, the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No. 772773) and the HiPEAC Network of Excellence. Pedro Benedicte and Jaume Abella have been partially supported by the MINECO under FPU15/01394 grant and Ramon y Cajal postdoctoral fellowship number RYC-2013-14717 respectively. ; Peer Reviewed ; Postprint (author's final draft)

Error theorists argue that there is a fundamental mistake, an error of some kind, at the heart of commonsense morality. They have drawn on evolutionary theory to support some of their claims. This article looks at four different models of evolution and assesses what implications can be drawn from them concerning commonsense morality and the claims of the error theorists Mackie, Ruse and Joyce. The author first spells out the main points of error theory, then discusses how recent proponents of error theory have attempted to join error theory about ethics with an evolutionary perspective. Finally, to assess their claims, the author examines what the models of evolution put forward by Darwin, Dawkins, Gould and Haught imply about error theory in ethics.

As implementation technology shrinks, the presence of errors in cache memories is becoming an increasing issue in all computing domains. Critical systems, e.g. space and automotive, are specially exposed and susceptible to reliability issues. Furthermore, hardware designs in these systems are migrating to multilevel cache multicore systems, in which write-through first level data (DL1) caches have been shown to heavily harm average and guaranteed performance. While write-back DL1 caches solve this problem they come with their own challenges: they need Error Correction Codes (ECC) to tolerate soft errors, but implementing DL1 ECC in simple embedded micro-controllers requires either complex hardware to squash instructions consuming erroneous data, or delayed delivery of data to correct potential errors, which impacts performance even if such process is pipelined. In this paper we present a low-complexity hardware mechanism to anticipate data fetch and error correction in DL1 so that both (1) correct data is always delivered, but (2) avoiding additional delays in most of the cases. This achieves both high guaranteed performance and an effective solutions against errors. ; This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P, the European Research Council (ERC) under the European Union's Horizon 2020 research and innovation programme (grant agreement No. 772773) and the HiPEAC Network of Excellence. Pedro Benedicte and Jaume Abella have been partially supported by the MINECO under FPU15/01394 grant and Ramon y Cajal postdoctoral fellowship number RYC-2013-14717 respectively. ; Peer Reviewed ; Postprint (author's final draft)